NIOS2 FPGA work

At work I got assigned to write a very simple control system for a device we are making a prototype of. For various reasons, the designers choice to use an FPGA with a soft-core processor. What this means is that the processor is simply made from available gates on the FPGA. A fascinating concept and one that has advantages such as adding a new instruction to the processor to support some weird thing you are doing.

In my case it was just a matter of sending and receiving some serial messages, controlling some SPI devices, and tickling some IO pins are appropriate times. How hard could that be?

When each development iteration takes 25 minutes to compile, when all you have initially (till you get the UART to work) is one IO pin to blink for debugging, and the stock C library is too fat to fit into your available memory footprint, it can be very hard. For the whole week I have been working every waking hour trying to get ready for a demo early next week. And since I have the time to write this post, I succeeded late last night.

I still need to support the integration team over the weekend, but I should be able to get back to my own home projects soon.

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